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MP8762 high efficiency, 10a, 18v synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 1 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology description the MP8762 is a fully integrated high frequency synchronous rectified step-down switch mode converter. it offers a very compact solution to achieve 10a output current over a wide input supply range with excellent load and line regulation. the MP8762 operates at high efficiency over a wide output current load range. the MP8762 adopts constant-on-time (cot) control mode that provides fast transient response and eases loop stabilization. operation frequency can be programmed easily from 200khz to 1mhz by an external resistor and keeps nearly constant as input supply varies by the feedforward compensation. under voltage lockout is internally set at 4.1v, but can be increased by programming the threshold with a resistor network on the enable pin. the output voltage startup ramp is controlled by the soft start pin. an open drain power good signal indicates the output is within its nominal voltage range. full integrated protection features include ocp, ovp and thermal shutdown. the MP8762 requires a minimum number of readily available standard external components and are available in qfn 3x4 package. features ? 2.5v to 5v operating input range with external 5v bias ? 4.5v to 18v operating input range with internal bias ? 10a output current ? low r ds (on) internal power mosfets ? proprietary switching loss reduction technique ? adaptive cot for ultrafast transient response ? 1.5% reference voltage over -40 c to +125 c junction temperature range ? programmable soft start time ? pre-bias start up ? programmable switching frequency from 200khz to 1mhz ? non-latch ocp, ovp protection and thermal shutdown ? output adjustable from 0.611v to 13v applications ? set-top boxes ? xdsl modem/dslam ? small-cell base stations ? personal video recorders ? flat panel television and monitors ? distributed power systems all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application in freq vcc en pgnd bst fb sw MP8762 v in on/off c1 r freq c5 c3 l1 r4 c4 r1 r2 c2 r3 pg agnd ss v out c6
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 2 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. ordering information part number package top marking MP8762gl * qfn(3x4mm) MP8762 MP8762gle ** 16-pin qfn(34mm) MP8762e * for tape & reel, add suffix ?z (e.g. MP8762gl?z) ** for tape & reel, add suffix ?z (e.g. MP8762gle?z) note: the 16-pin qfn package is preferred and recommended for new designs package reference top view pgnd 4 in 2 bst 11 12 13 910 8 7 6 vcc pg agnd ss fb freq en pgnd sw 3 1 sw 5 top view 13-pin qfn (3x4mm) 16-pin qfn (3x4mm) absolute maxi mum ratings (1) supply voltage v in ....................................... 21v v sw ........................................-0.3v to v in + 0.3v v sw (30ns)...................................-3v to v in + 3v v bst ...................................................... v sw + 6v enable current i en (2) ................................ 2.5ma all other pins .................................?0.3v to +6v continuous power dissipation (t a =+25 ) (3) qfn3x4?????????.?..????2.7w junction temperature ...............................150 c lead temperature ....................................260 c storage temperature............... -65 c to +150 c recommended operating conditions (4) supply voltage v in ...........................4.5v to 18v output voltage v out .....................0.611v to 13v i en .............................................................. 1ma operating junction temp. (t j ). -40c to +125c follow layout recommendation on page 36 for best performance thermal resistance (5) ja jc qfn (3x4mm) ......................... 46 ....... 9.... c/w notes: 1) exceeding these ratings may damage the device. 2) refer to the section ?configuring the en control?. 3) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 4) the device is not guaranteed to function outside of its operating conditions. 5) measured on jesd51-7, 4-layer pcb.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 3 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics v in = 12v, t j = +25 c, unless otherwise noted. parameters symbol condition min typ max units supply current supply current (shutdown) i in v en = 0v 0 1 a supply current (quiescent) i in v en = 2v, v fb = 1v 760 860 960 a mosfet high-side switch on resistance hs rds-on t j =25 c 21 m ? low-side switch on resistance ls rds-on t j =25 c 7 m ? switch leakage sw lkg v en = 0v, v sw = 0v or 12v 0 1 a current limit low-side valley current limit (6) i limit_valley 9.5 11 12.5 a low-side negative current limit (6) i limit_negative -4 -2.5 -1 a timer minimum on time (6) t on_min 20 30 40 ns one-shot on time t on r freq =453k ? , v out =1.2v 250 ns minimum off time (6) t off_min 50 100 150 ns over-voltage and under-voltage protection ovp latch threshold (6) v ovp_latch 127% 130% 133% v fb ovp non-latch threshold v ovp_non- latch 117% 120% 123% v fb ovp delay t ovp 2 s uvp threshold (6) v uvp 50% v fb reference and soft start t j = -40 c to +125 c (7) 602 611 620 reference voltage v ref t j = +25 c 605 611 617 mv feedback current i fb v fb = 650mv 50 100 na soft start charging current i ss v ss =0v 16 20 25 a enable and uvlo enable input low voltage vil en 1.1 1.3 1.5 v enable hysteresis v en-hys 250 mv v en = 2v 5 enable input current i en v en = 0v 0 a
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 4 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics (continued) v in = 12v, t j = +25 c, unless otherwise noted. parameters symbol condition min typ max units vcc regulator vcc under voltage lockout threshold rising vcc vth 3.8 v vcc under voltage lockout threshold hysteresis vcc hys 500 mv vcc regulator v cc 4.8 v vcc load regulation icc=5ma 0.5 % power good power good rising threshold pg vth-hi 87% 91% 94% v fb power good falling threshold pg vth-lo 80% v fb power good lower to high delay pg td 2.5 ms power good sink current capability v pg sink 4ma 0.4 v power good leakage current i pg_leak v pg = 3.3v 10 100 na thermal protection thermal shutdown t sd note 5 150 c thermal shutdown hysteresis 25 c note: 6) guaranteed by design. 7) not production test, guar anteed by characterization
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 5 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. pin functions pin # 13-pin qfn pin# 16-pin qfn name description 1 1 en enable pin. en is a digital input that turns the regulator on or off. drive en high to turn on the regulator, drive it lo w to turn it off. connect en to in through a pull-up resistor or a resistiv e voltage divider for automatic startup. do not float this pin. see enable control section for more details. 2 2 freq frequency set during ccm operation. a resistor connected between freq and in is required to set the switching frequency. the on time is determined by the input voltage and the re sistor connected to the freq pin. in connect through a resistor is used for line feed-forward and makes the frequency basically constant during in put voltage?s variation. an optional 1nf decoupling capacitor can be added to improve any switching frequency jitter that may be present. 3 3 fb feedback. an external resistor divider from the output to gnd, tapped to the fb pin, sets the output voltage. it is recommended to place the resistor divider as close to fb pin as possible. vias should be avoided on the fb traces. 4 4 ss soft start. connect on external capacitor to program the soft start time for the switch mode regulator. 5 5 agnd analog ground. select this pin as the control circuit reference point. 6 6 pg power good output, the output of this pin is an open drain signal and a pull- up resistor connected to a dc voltage is required to indicate high if the output voltage is higher than 91% of th e nominal voltage. there is a delay from fb 91% to pgood goes high. 7 7 vcc internal 5v ldo output. the driver and c ontrol circuits are powered from this voltage. decouple with a minimum 1f ceramic capacitor as close to the pin as possible. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. 8 8 bst bootstrap. a capacitor connected between sw and bs pins is required to form a floating supply across the high-side switch driver. 9,10 15, 16 sw switch output. connect this pin to the inductor and bootstrap capacitor. this pin is driven up to the v in voltage by the high-side switch during the on-time of the pwm duty cycle. the inductor current drives the sw pin negative during the off-time. the on-resistance of the low-side switch and the internal schottky diode fixes the negative voltage. use wide pcb traces to make the connection. 11,12 10,11,12, 13 pgnd system ground. this pin is the re ference ground of the regulated output voltage. for this reason care must be taken in pcb layout. use wide pcb traces to make the connection. 13 9, 14 in supply voltage. the in pin supplies power for internal mosfet and regulator. the MP8762 operates from a +2.5v to +5v input rail with 5v external bias and a +4.5v to +18v input rail with internal bias. a n input capacitor is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 6 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical characteristics vin = 12v, v out = 1v, l = 1h, t a = 25oc, unless otherwise noted.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 7 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical characteristics (continued) v in = 12v, v out = 1v, l = 1h, t a = 25oc, unless otherwise noted. 4 4.2 4.4 4.6 4.8 5 -50 0 50 100 150 200 300 400 500 600 700 -50 0 50 100 150 100 300 500 700 900 1100 100 300 500 700 900 0 100 200 300 400 500 600 02.5 57.510 0 5 10 15 20 25 30 35 0246810 10 12 14 16 18 20 0 5 10 15 20 25 5 7 9 11 13 15 0 5 10 15 20 25 600 605 610 615 620 -50 0 50 100 150
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 8 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics v in = 12v, v out = 1v, l = 1h, t a = 25oc, unless otherwise noted.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 9 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1v, l=1h, t a =+25c, unless otherwise noted. v out 500mv/div. pg 5v/div. en 5v/div. v out 500mv/div. pg 5v/div. en 5v/div. v out 500mv/div. v in 10v/div. sw 10v/div. i l 2a/div. v out 500mv/div. v in 10v/div. sw 10v/div. i l 10a/div. start up through v in i out = 0a start up through v in i out = 10a v out 500mv/div. v in 10v/div. sw 10v/div. i l 10a/div. v out 1v/div. v in 5v/div. sw 10v/div. i l 10a/div. shutdown through v in i out = 0a shutdown through v in i out = 10a v out 500mv/div. en 5v/div. sw 10v/div. i l 2a/div. start up through en i out = 0a v out 500mv/div. en 5v/div. sw 10v/div. i l 10a/div. v out 500mv/div. en 5v/div. sw 10v/div. i l 2a/div. start up through en i out = 10a shutdown through en i out = 0a
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 10 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, v out =1v, l=1h, t a =+25c, unless otherwise noted. v out (ac) 100mv/div. i l 5a/div. v out (ac) 500mv/div. i l 10a/div. sw 10v/div. v out 500mv/div. i l 2a/div. sw 10v/div. v out 1v/div. en 5v/div. sw 10v/div. i l 10a/div. short circuit protection thermal shutdown i out = 0a v out 500mv/div. i l 2a/div. sw 10v/div. thermal recovery i out = 0a
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 11 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. block diagram 0. 6v 0.3v 0.75 v figure 1?functional block diagram
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 12 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. operation pwm operation the MP8762 is fully integrated synchronous rectified step-down switch mode converter. constant-on-time (cot) control is employed to provide fast transient response and easy loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (v fb ) is below the reference voltage (v ref ), which indicates insufficient output voltage. the on period is determined by the input voltage and the frequency-set resistor as follows: 4 . 0 ) v ( v ) k ( r 3 . 5 ) ns ( t in freq on ? = (1) after the on period elapses, the hs-fet is turned off, or becomes off state. it is turned on again when v fb drops below v ref . by repeating operation this way, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) is turned on when the hs-fet is in its off state to minimize the conduction loss. there will be a dead short between input and gnd if both hs-fet and ls-fet are turned on at the same time. it?s called shoot-through. in order to avoid shoot-through, a dead-time (dt) is internally generated between hs-fet off and ls- fet on, or ls-fet off and hs-fet on. heavy-load operation figure 2?heavy load operation when the output current is high and the inductor current is always above zero amps, it is called continuous-conduction-mode (ccm). the ccm mode operation is shown in figure 2. when v fb is below v ref , hs-fet is turned on for a fixed interval which is determined by one- shot on- timer as equation 1 shown. when the hs-fet is turned off, the ls-fet is turned on until next period. in ccm mode operation, the switching frequency is fairly constant and it is called pwm mode. light-load operation as the load decreases, the inductor current decreases too. when the inductor current touches zero, the operation is transited from continuous-conduction-mode (ccm) to discontinuous-conduction-mode (dcm). the light load operation is shown in figure 3. when v fb is below v ref , hs-fet is turned on for a fixed interval which is determined by one- shot on-timer as equation 1 shown. when the hs-fet is turned off, the ls-fet is turned on until the inductor current reaches zero. in dcm operation, the v fb does not reach v ref when the inductor current is approaching zero. the ls-fet driver turns into tri-state (high z) whenever the inductor current reaches zero. a current modulator takes over the control of ls-fet and limits the inductor current to less than -1ma. hence, the output capacitors discharge slowly to gnd through ls- fet. as a result, the efficiency at light load condition is greatly improved. at light load condition, the hs-fet is not turned on as frequently as at heavy load condition. this is called skip mode. at light load or no load condition, the output drops very slowly and the MP8762 reduces the switching frequency naturally and then high efficiency is achieved at light load. figure 3?light load operation
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 13 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. as the output current increases from the light load condition, the time period within which the current modulator regulates becomes shorter. the hs-fet is turned on more frequently. hence, the switching frequency increases correspondingly. the output current reaches the critical level when the current modulator time is zero. the critical level of the output current is determined as follows: in sw out out in out v f l 2 v ) v v ( i ? = (2) where f sw is the switching frequency. it turns into pwm mode once the output current exceeds the critical level. after that, the switching frequency stays fairly constant over the output current range. switching frequency the selection of switching frequency is a tradeoff between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and capacitance to maintain low output voltage ripple. for MP8762 the on time can be set using freq pin, then the frequency is set in steady state operation at ccm mode. adaptive constant-on-time (cot) control is used in MP8762 and there is no dedicated oscillator in the ic. connect freq pin to in pin through resistor r freq and the input voltage is feed- forwarded to the one-shot on-time timer through the resistor r freq . when in steady state operation at ccm, the duty ratio is kept as v out /v in . hence the switching frequency is fairly constant over the input voltage range. the switching frequency can be set as follows: ) ns ( t ) v ( v ) v ( v 4 . 0 ) v ( v ) k ( r 3 . 5 10 ) khz ( f delay out in in freq 6 sw + ? = (3) where t delay is the comparator delay. it?s about 40ns. generally, the MP8762 is set for 200khz to 1mhz application. it is optimized to operate at high switching frequency with high efficiency. high switching frequency makes it possible to utilize small sized lc filter components to save system pcb space. jitter and fb ramp slope figure 4 and figure 5 show jitter occurring in both pwm mode and skip mode. when there is noise in the v fb downward slope, the on time of hs-fet deviates from its intended location and produces jitter. it is necessary to understand that there is a relationship between a system?s stability and the steepness of the v fb ripple?s downward slope. the slope steepness of the v fb ripple dominates in noise immunity. the magnitude of the v fb ripple doesn?t affect the noise immunity directly. figure 4?jitter in pwm mode figure 5?jitter in skip mode ramp with large esr capacitor in the case of poscap or other types of capacitor with lager esr is applied as output capacitor, the esr ripple dominates the output ripple, and the slope on the fb is quite esr related. figure 6 shows an equivalent circuit in pwm mode with the hs-fet off and without an external ramp circuit. turn to application information section for design steps with large esr capacitors.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 14 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. r1 r2 esr poscap sw v out l fb figure 6?simplified circuit in pwm mode without external ramp compensation to realize the stability when no external ramp is applied, usually the esr value should be chosen as follow: out on sw esr c 2 t 7 . 0 t r + (4) where t sw is the switching period. ramp with small esr capacitor when the output capacitors are ceramic ones, the esr ripple is not high enough to stabilize the system, and external ramp compensation is needed. skip to application information section for design steps with small esr caps. r1 r2 ceramic sw fb v out l r4 c4 i r4 i c4 i fb r9 figure 7?simplified circuit in pwm mode with external ramp compensation in pwm mode, an equivalent circuit with hs-fet off and the use of an external ramp compensation circuit (r4, c4) is simplified in figure 7. the external ramp is derived from the inductor ripple current. if one chooses c4, r9, r1 and r2 to meet the following condition: ? ? ? ? ? ? + + < 9 r 2 r 1 r 2 r 1 r 5 1 4 c f 2 1 sw (5) where: 4 c fb 4 c 4 r i i i i + = (6) and the ramp on the v fb can then be estimated as: ? ? ? ? ? ? + ? = 9 r 2 r // 1 r 2 r // 1 r t 4 c 4 r v v v on out in ramp (7) the downward slope of the v fb ripple then follows: 4 c 4 r v t v v out off ramp 1 slope ? = = (8) as can be seen from equation 8, if there is instability in pwm mode, we can reduce either r4 or c4. if c4 can not be reduced further due to limitation from equation 5, then we can only reduce r4. for a stable pwm operation, the v slope1 should be design follow equation 9. sw on 3 esr out out slope1 out out sw on tt rc i10 0.7 2 vv 2lc t t ? +? ? + ? (9) where i out is the load current. in skip mode, the downward slope of the v fb ripple is almost same whether the external ramp is used or not. fig.8 shows the simplified circuit of the skip mode when both the hs-fet and ls- fet are off. r1 r2 c out fb v out r out figure 8?simplified circuit in skip mode the downward slope of the v fb ripple in skip mode can be determined as follows: out out ref 2 slope c ] r // ) 2 r 1 r [( v v + ? = (10) where r out is the equivalent load resistor. as described in fig.5, v slope2 in the skip mode is lower than that is in the pwm mode, so it is
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 15 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. reasonable that the jitter in the skip mode is larger. if one wants a system with less jitter during ultra light load condition, the values of the v fb resistors should not be too big, however, that will decrease the light load efficiency. configuring the en control en high to turn on the regulator and en low to turn it off. do not float the pin. for automatic start-up the en pin can be pulled up to input voltage through a resistive voltage divider. choose the values of the pull-up resistor (r up from v in pin to en pin) and the pull-down resistor(r down from en pin to gnd) to determine the automatic start-up voltage: ) v ( r ) r r ( 45 . 1 v down down up start in + = ? (11) for example, for r up =100k ? and r down =51k ? , the v in-start is set at 4.29v. to avoid noise, a 10nf ceramic capacitor from en to gnd is recommended. there is an internal zener diode on the en pin, which clamps the en pin voltage to prevent it from running away. the maximum pull up current assuming a worst case 6v internal zener clamp should be less than 1ma. therefore, when en is driven by an external logic signal, the en voltage should be lower than 6v; when en is connected with v in through a pull-up resistor or a resistive voltage divider, the resistance selection should ensure the maximum pull up current less than 1ma. if using a resistive voltage divider and v in higher than 6v, the allowed minimum pull-up resistor r up should meet the following equation: in up down v6v 6v 1ma rr ? ? (12) especially, just using the pull-up resistor r up (the pull-down resistor is not connected), the v in-start is determined by vcc uvlo, and the minimum resistor value is: in up v6v r() 1ma ? ? (13) a typical pull-up resistor is 100k ? . soft start the MP8762 employs soft start (ss) mechanism to ensure smooth output during power-up. when the en pin becomes high, an internal current source (20 a) charges up the ss capacitor. the ss capacitor voltage takes over the ref voltage to the pwm comparator. the output voltage smoothly ramps up with the ss voltage. once the ss voltage reaches the same level as the ref voltage, it keeps ramping up while v ref takes over the pwm comparator. at this point, the soft start finishes and it enters into steady state operation. the ss capacitor value can be determined as follows: () ( ) ( ) () = ss ss ss ref tmsi a cnf vv (14) if the output capacitors have large capacitance value, it?s not recommended to set the ss time too small. otherwise, it?s easy to hit the current limit during ss. a minimum value of 4.7nf should be used if the output capacitance value is larger than 330 f. pre-bias startup the MP8762 has been designed for monotonic startup into pre-biased loads. if the output is pre- biased to a certain voltage during startup, the ic will disable the switching of both high-side and low-side switches until the voltage on the soft- start capacitor exceeds the sensed output voltage at the fb pin. power good (pg) the MP8762 have power-good (pg) output. the pg pin is the open drain of a mosfet. it should be connected to vcc or other voltage source that is less 5.5v through a pull-up resistor (e.g. 100k). after the input voltage is applied, the mosfet is turned on so that the pg pin is pulled to gnd before ss is ready. after fb voltage reaches 91% of ref voltage, the pg pin is pulled high after a 2.5ms delay. when the fb voltage drops to 80% of ref voltage or exceeds 120% of the nominal ref voltage, the pg pin will be pulled low.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 16 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. if the MP8762 doesn?t work, the pg pin is also pulled low even though this pin is tied to an external dc source through a pull-up resistor(e.g. 100k). over-current protection (ocp) the MP8762 features three current limit levels for over-current conditions: high-side peak current limit, low-side valley current limit and low-side negative current limit. high-side peak current limit: MP8762 has cycle- by-cycle over-current limiting function. during hs-fet on state, the inductor current is monitored. when the sensed inductor current hits the peak current limit, the hs limit comparator (shown in figure 1) turns over, the device enters over-current protection mode immediately, turns off hs-fet and turns on ls-fet. low-side valley current limit: during ls-fet on state, the inductor current is also monitored. at the end of off time, the ls-fet sourcing current is compared to the internal positive valley current limit. if the ls-fet sourcing current is exceeded the valley current limit, the hs-fet is not turned on and the ls-fet keeps on for the next on time. until the ls-fet sourcing current is below the valley current limit the hs-fet is turned on again. during over-current protection, the device tries to recover from over-current fault with hiccup mode, that means the chip will disable output power stage, discharge soft-start cap and then automatically try to soft-start again. if the over- current condition still holds after soft-start ends, the device repeats this operation cycle till over- current conditions disappear and then output rises back to regulation level. so the ocp is non- latch protection. low-side negative current limit: if the ls-fet sensed negative current exceeds the negative current limit, e.g. over-voltage protection (ovp) the ls-fet is turned off immediately for the the rest of off time. in this situation, both mosfets are off until the end of a fixed interval. the body diode of hs-fet conducts the inductor current for the fixed time. over -voltage protection (ovp) the MP8762 monitors the output voltage through a resistor divider feedback (fb) voltage to detect over-voltage on the output. if the fb voltage is higher than nominal ref voltage but lower than 120% of the ref voltage (0.611v), both mosfets are off, when the fb voltage is higher than 120% but lower than 130% of the ref voltage, the ls-fet will be turned on while the hs-fet keeps off. the ls-fet keeps on until the fb voltage drops below 110% of the ref voltage or the low-side negative current limit is trigged. if the fb voltage is higher than 130% of the ref voltage, then the device is latched off. cycling the input power supply or en is needed to restart. uvlo protection the MP8762 has under-voltage lock-out protection (uvlo). when the vcc voltage is higher than the uvlo rising threshold voltage, the MP8762 will be powered up. it shuts off when the vcc voltage is lower than the uvlo falling threshold voltage. this is non-latch protection. the MP8762 is disabled when the vcc voltage falls below 3.3 v. if an application requires a higher under-voltage lockout (uvlo), use the en pin as shown in figure 9 to adjust the startup input voltage by using two external resistors. it is recommended to use the enable resistors to set the input voltage falling threshold (v stop ) above 3.6 v. the rising threshold (v start ) should be set to provide enough hysteresis to allow for any input supply variations. en comparator r up r down in en figure 9?adjustable uvlo
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 17 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. thermal shutdown thermal shutdown is employed in the MP8762. the junction temperature of the ic is internally monitored. if the junction temperature exceeds the threshold value (minimum 150oc), the converter shuts off. this is a non-latch protection. there is about 25oc hysteresis. once the junction temperature drops to about 125oc, it initiates a soft startup.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 18 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. application information setting the output voltage-large esr caps for applications that electrolytic capacitor or pos capacitor with a controlled output of esr is set as output capacitors. the output voltage is set by feedback resistors r1 and r2. as figure 10 shows. r1 r2 esr poscap sw v out l fb figure10?simplified circuit of pos capacitor first, choose a value for r2. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? - 50k ? for r2, using a comparatively larger r2 when v out is low, and a smaller r2 when v out is high. then r1 is determined as follow with the output ripple considered: out out ref ref 1 vvv 2 r1 r 2 v ? ? = (15) out v is the output ripple determined by equation 24. setting the output voltage-small esr caps r1 r2 ceramic sw fb v out l r9 r4 c4 figure11?simplified circuit of ceramic capacitor when low esr ceramic capacitor is used in the output, an external voltage ramp should be added to fb through resistor r4 and capacitor c4.the output voltage is influenced by ramp voltage v ramp besides resistor divider as shown in figure 11. the v ramp can be calculated as shown in equation 7. r2 should be chosen reasonably, a small r2 will lead to considerable quiescent current loss while too large r2 makes the fb noise sensitive. it is recommended to choose a value within 5k ? -50k ? for r2, using a comparatively larger r2 when v out is low, and a smaller r2 when v out is high. and the value of r1 then is determined as follow: 9 r 4 r 2 r v v v 2 r 1 r ) avg ( fb out ) avg ( fb + ? ? = (16) the v fb(avg) is the average value on the fb. v fb(avg) varies with the v in , v out , and load condition, etc.. its value on the skip mode would be lower than that of the pwm mode, which means the load regulation is strictly related to the v fb(avg) . also the line regulation is related to the v fb(avg) ,if one wants to gets a better load or line regulation, a lower v ramp is suggested once it meets equation 9. for pwm operation, v fb(avg) value can be deduced from equation 17. 9 r 2 r // 1 r 2 r // 1 r v 2 1 v v ramp ref ) avg ( fb + + = (17) usually, r9 is set to 0 ? , and it can also be set following equation 18 for a better noise immunity. it also should be set to be 5 timers smaller than r1//r2 to minimize its influence on v ramp . 1r1r2 r9 5r1r2 < + (18) using equation 16 and 17 to calculate the output voltage can be complicated. to simplify the calculation of r1 in equation 11, a dc-blocking capacitor c dc can be added to filter the dc influence from r4 and r9. figure 12 shows a simplified circuit with external ramp compensation and a dc-blocking capacitor. with this capacitor, r1 can easily be obtained by using equation 19 for pwm mode operation.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 19 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. 2 r v 2 1 v v 2 1 v v 1 r ramp ref ramp ref out + ? ? = (19) c dc is suggested to be at least 10 times larger than c4 for better dc blocking performance, and should be not larger than 0.47uf considering start up performance. in case one wants to use larger c dc for a better fb noise immunity, combined with reduced r1 and r2 to limit the c dc in a reasonable value without affecting the system start up. be noted that even when the cdc is applied, the load and line regulation are still v ramp related. r1 r2 ceramic sw fb v out l c dc r4 c4 figure12?simplified circuit of ceramic capacitor with dc blocking capacitor input capacitor the input current to the step-down converter is discontinuous. therefore, a capacitor is required to supply the ac current to the step-down converter while maintaining the dc input voltage. ceramic capacitors are recommended for best performance. in the layout, it?s recommended to put the input capacitors as close to the in pin as possible. the capacitance varies significantly over temperature. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable over temperature. the capacitors must also have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated as follows: ) v v 1 ( v v i i in out in out out cin ? = (20) the worst-case condition occurs at v in = 2v out , where: 2 i i out cin = (21) for simplification, choose the input capacitor whose rms current rating is greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is input voltage ripple requirement in the system design, choose the input capacitor that meets the specification the input voltage ripple can be estimated as follows: ) v v 1 ( v v c f i v in out in out in sw out in ? = (22) the worst-case condition occurs at v in = 2v out , where: in sw out in c f i 4 1 v = (23) output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltage ripple can be estimated as: ) c f 8 1 r ( ) v v 1 ( l f v v out sw esr in out sw out out + ? = (24) in the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. the output voltage ripple is mainly caused by the capacitance. for simplification, the output voltage ripple can be estimated as: ) v v 1 ( c l f 8 v v in out out 2 sw out out ? = (25) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4 following equation 5, 8 and 9.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 20 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. in the case of poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr is high enough to stabilize the system. therefore, an external ramp is not needed. a minimum esr value around 12m ? is required to ensure stable operation of the converter. for simplification, the output ripple can be approximated as: esr in out sw out out r ) v v 1 ( l f v v ? = (26) inductor the inductor is required to supply constant current to the output load while being driven by the switching input voltage. a larger value inductor will result in less ripple current and lower output ripple voltage. however, a larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. a good rule for determining the inductor value is to allow the peak-to-peak ripple current in the inductor to be approximately 30~40% of the maximum switch current limit. also, make sure that the peak inductor current is below the maximum switch current limit. the inductance value can be calculated as: ) v v 1 ( i f v l in out l sw out ? = (27) where i l is the peak-to-peak inductor ripple current. choose an inductor that will not saturate under the maximum inductor peak current. the peak inductor current can be calculated as: ) v v 1 ( l f 2 v i i in out sw out out lp ? + = (28) the inductors listed in table 1 are highly recommended for the high efficiency they can provide. table 1?inductor selection guide part number manufacturer inductance (h) dcr (m ? ) current rating (a) dimensions l x w x h (mm 3 ) switching frequency (khz) pcmc-135t-r68mf cyntec 0. 68 1.7 34 13.5 x 12.6 x 4.8 600 fda1254-1r0m toko 1 2 25.2 13.5 x 12.6 x 5.4 300~600 fda1254-1r2m toko 1.2 2.05 20.2 13.5 x 12.6 x 5.4 300~600 typical design parameter tables the following tables include recommended component values for typical output voltages (1v, 2.5v, 3.3v) and switching frequencies (300khz, 500khz, and 800khz). refer to tables 2-4 for design cases without external ramp compensation and tables 5-7 for design cases with external ramp compensation. external ramp is not needed when high-esr capacitors, such as electrolytic or poscaps are used. external ramp is needed when low-esr capacitors, such as ceramic capacitors are used. for cases not listed in this datasheet, a calculator in excel spreadsheet can also be requested through a local sales representative to assist with the calculation. table 2?f sw =300khz, v in =12v v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1 2.2 17.4 26.1 604 2.5 2.2 45.3 14.3 1500 3.3 2.2 47 10.5 2000 table 3?f sw =500khz, v in =12v v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1 1 17.4 26.1 357 2.5 1 45.3 14.3 887 3.3 1 47 10.5 1200
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 21 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. table 4? f sw =800khz, v in =12v v out (v) l ( h) r1 (k ? ) r2 (k ? ) r7 (k ? ) 1 1 17.4 26.1 220 2.5 1 45.3 14.3 549 3.3 1 47 10.5 732 table 5?f sw =300khz, v in =12v v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1 2.2 16.9 26.1 390 330 604 2.5 3.3 46.4 14.3 1000 330 1500 3.3 3.3 48.7 10.5 1000 330 2000 table 6?f sw =500khz, v in =12v v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1 1 16.9 26.1 560 180 357 2.5 1 46.4 14.3 1300 150 887 3.3 1 48.7 10.5 910 220 1200 table 7? f sw =800khz, v in =12v v out (v) l ( h) r1 (k ? ) r2 (k ? ) r4 (k ? ) c4 (pf) r7 (k ? ) 1 1 16.9 26.1 1100 100 220 2.5 1 46.4 14.3 2000 100 549 3.3 1 48.7 10.5 1100 120 732
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 22 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical application (7) in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 357k r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 13.7k 20k v out 0.1uf c2a c2b 0.1uf 220uf/20m + figure 13 ? typical application circuit with no external ramp v in =12v, v out =1v, i out =10a, f sw =500khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 357k r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 330k 220pf 13.7k 20k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 14 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1v, i out =10a, f sw =500khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 357k r5 100k 1uf 100k 0 1uh, toko fdu1250c-1r0m 330k 220pf 13.7k 20k c dc 10nf v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 15 ? typical application circuit with low esr ceramic capacitor and dc-blocking capacitor . v in =12v, v out =1v, i out =10a, f sw =500khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 23 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. figure 16 ? efficiency curve v out =1v, i out =0.01a-10a, f sw =500khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 604k r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 270k 390pf 13.7k 20k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 17 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1v, i out =10a, f sw =300khz figure 18 ? efficiency curve v out =1v, i out =0.01a-10a, f sw =300khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 24 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 220k r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 301k 220pf 28k 40.2k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 19 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1v, i out =10a, f sw =800khz output current (a) 30 40 50 60 70 80 90 100 0.01 0.1 1 10 figure 20 ? efficiency curve v out =1v, i out =0.01a-10a, f sw =800khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 475k r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 330k 330pf 12.7k 40.2k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 21 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =0.8v, i out =10a, f sw =300khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 25 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. figure 22 ? efficiency curve v out =0.8v, i out =0.01a-10a, f sw =300khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 287k r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 330k 220pf 12.7k 40.2k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 23 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =0.8v, i out =10a, f sw =500khz figure 24 ? efficiency curve v out =0.8v, i out =0.01a-10a, f sw =500khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 26 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 715k r5 100k 1uf 100k r3 0 2.2uh, toko fda1254-2r2m 330k 330pf 20.5k 20k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 25 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.2v, i out =10a, f sw =300khz figure 26 ? efficiency curve v out =1.2v, i out =0.01a-10a, f sw =300khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 432k r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 220k 330pf 10k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 27 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.2v, i out =10a, f sw =500khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 27 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. figure 28 ? efficiency curve v out =1.2v, i out =0.01a-10a, f sw =500khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 270k r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 220k 220pf 10k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 29 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.2v, i out =10a, f sw =800khz figure 30 ? efficiency curve v out =1.2v, i out =0.01a-10a, f sw =800khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 28 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 887k r5 100k 1uf 100k r3 0 2.2uh, toko fda1254-2r2m 470k 470pf 15k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 31 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.5 v, i out =10a, f sw =300khz figure 32 ? efficiency curve v out =1.5v, i out =0.01a-10a, f sw =300khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 536k r5 100k 1uf 100k r3 0 1.2uh, toko fda1254-1r2m 470k 330pf 15.4k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 33 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.5 v, i out =10a, f sw =500khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 29 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. figure 34 ? efficiency curve v out =1.5v, i out =0.01a-10a, f sw =500khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 332k r5 100k 1uf 100k r3 0 1.2uh, toko fda1254-1r2m 470k 220pf 15.4k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 35 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.5 v, i out =10a, f sw =800khz figure 36 ? efficiency curve v out =1.5v, i out =0.01a-10a, f sw =800khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 30 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 1.1m r5 100k 1uf 100k r3 0 2.2uh, toko fda1254-2r2m 470k 220pf 19.6k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 37 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.8 v, i out =10a, f sw =300khz figure 38 ? efficiency curve v out =1.8v, i out =0.01a-10a, f sw =300khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 634k r5 100k 1uf 100k r3 0 2.2uh, toko fda1254-2r2m 470k 220pf 21k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 39 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.8 v, i out =10a, f sw =500khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 31 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. figure 40 ? efficiency curve v out =1.8v, i out =0.01a-10a, f sw =500khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 402k r5 100k 1uf 100k r3 0 2.2uh, toko fda1254-2r2m 470k 220pf 21k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 41 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =1.8 v, i out =10a, f sw =800khz figure 42 ? efficiency curve v out =1.8v, i out =0.01a-10a, f sw =800khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 32 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 2m r5 100k 1uf 100k r3 0 2.2uh, toko fda1254-2r2m 470k 220pf 48.7k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 43 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =3.3 v, i out =10a, f sw =300khz figure 44 ? efficiency curve v out =3.3v, i out =0.01a-10a, f sw =300khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 1.2m r5 100k 1uf 100k r3 0 2.2uh, toko fda1254-2r2m 470k 220pf 48.7k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 45 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =3.3 v, i out =10a, f sw =500khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 33 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. figure 46 ? efficiency curve v out =3.3v, i out =0.01a-10a, f sw =500khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 715k r5 100k 1uf 100k r3 0 2.2uh, toko fda1254-2r2m 470k 220pf 48.7k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 47 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =3.3 v, i out =10a, f sw =800khz figure 48 ? efficiency curve v out =3.3v, i out =0.01a-10a, f sw =800khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 34 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 2.7m r5 100k 1uf 100k r3 0 3.3uh, toko fda1254-3r3m 470k 330pf 82.5k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 49 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =5 v, i out =10a, f sw =300khz figure 50 ? efficiency curve v out =5v, i out =0.01a-10a, f sw =300khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 1.8m r5 100k 1uf 100k r3 0 3.3uh, toko fda1254-3r3m 470k 330pf 84.5k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 51 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =5 v, i out =10a, f sw =500khz
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 35 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. figure 52 ? efficiency curve v out =5v, i out =0.01a-10a, f sw =500khz in freq vcc en pgnd bst fb sw MP8762 v in c1a r7 c5 c3 l1 r4 c4 r1 r2 r6 pg agnd ss c6 33nf 10uf c1b 10uf c1c 0.1uf c1d 0.1uf 1.1m r5 100k 1uf 100k r3 0 1uh, toko fdu1250c-1r0m 330k 220pf 82k 10k r9 100 v out c2a 22uf c2b 22uf c3c 22uf c2d 0.1uf 0.1uf c2e 0.1uf figure 53 ? typical application circuit with low esr ceramic capacitor v in =12v, v out =5 v, i out =10a, f sw =800khz figure 54 ? efficiency curve v out =5v, i out =0.01a-10a, f sw =800khz note: 8) the all application circuits? steady states are ok, but other performances are not tested.
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 36 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. layout recommendation 1. mps offers two packages, but recommends MP8762gle with its 16-pin qfn package for all new designs due to its smaller parasitical inductance. 2. place high current paths (gnd, in, and sw) very close to the device with short, direct and wide traces. 3. the 13-pin qfn package requires two copper in layers for better performance. respectively put at least a decoupling capacitor on both top and bottom layers and as close to the in and gnd pins as possible. also, several vias with 18mil diameter and 8mil hole- size are required to be placed under the device and near input capacitors to help on the thermal dissipation, also reduce the parasitic inductance. 4. put a decoupling capacitor as close to the vcc and agnd pins as possible. 5. keep the switching node (sw) plane as small as possible and far away from the feedback network. 6. place the external feedback resistors next to the fb pin. make sure that there are no vias on the fb trace. the feedback resistors should refer to agnd instead of pgnd. 7. keep the bst voltage path (bst, c3, and sw) as short as possible. 8. recommend strongly a four-layer layout to improve thermal performance. MP8762 figure 55?schematic for pcb layout guide in r3 r1 r3 r2 r3 r4 r3 c4 r3 c6 l1 r3 c2 vin gnd sw vout en freq fb ss agnd pg vcc bs t pgn d pgn d sw sw r3 c1a r3 r5 r3 c3 r3 c5 r3 r3 gnd r3 r freq r3 c1b top layer gnd inner1 layer gnd inner2 layer
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 37 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. r3 c1c vin gnd bottom layer figure 56?pcb layout guide for MP8762 pgnd pg n d in sw pgnd pgnd in sw b s t v c c p g a g n d s s f b f r e q e n c1d top layer inner1 layer inner2 layer bottom layer figure 57?pcb layout guide for mp8761gle (16-pin qfn)
MP8762 D 10a, 18v, synchronous step-down converter MP8762 rev. 1.4 www.monolithicpower.com 38 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information 13-pin qfn(3x4mm) side view bottom view note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeters max. 4) jedec reference is mo-220. 5) drawing is not to scale. top view recommended land pattern pin 1 id marking pin 1 id index area pin 1 id 0 .125 x45 T yp. 0.125 x45
MP8762 D 10a, 18v, synchronous step-down converter notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP8762 rev. 1.4 www.monolithicpower.com 39 11/4/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information 16-pin qfn (34mm) side view bottom view note: 1) all dimensions are in millimeters . 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeters max. 4) jedec reference is mo -220. 5) drawing is not to scale . top view recommended land pattern pin 1 id marking pin 1 id i ndex area pin 1 id 0.125 x 45 typ. 0. 125 x45

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